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Significant power consumption reduction has been achieved through partial CMOS logic implementation at the physical layer and low-voltage support at the logic layer.
SLIPHDMILPT is an IP core designed for mobile devices, reduced to a power consumption of 100mW or less (40mW or less for the physical layer only).
It can be easily integrated into SoCs such as HD TVs and AV receivers.
The HDMI receiver link IP core "SLISIHDMI" complies with the HDMI 1.3a standard, and when connected to the HDMI Receiver PHY IP SLIPHDMIR, it can most efficiently leverage the performance of the SLISIHDMIR HDMI Rx IP. Additionally, it is possible to customize the functions of the SLISIHDMIR HDMI Rx IP according to your requirements. For more details, please contact us.
By connecting with "SLIPHDMIR," it is possible to most efficiently extract performance and characteristics.
SLISHDMIR is an IP core for HDMI receiver link compliant with the HDMI 1.3a standard.
Achieving a maximum transfer rate of 300MB/s for UHS-II with low power consumption through proprietary technology.
This is a PHY IP solution for the ultra-high-speed interface "UHS-II" that can be used with the new SD card standards SDXC and SDHC.
